Date: Jan 2, 2019
Ericsson is thrilled to announce the opening of our brand new ASIC/SoC design center located in the heart of Austin, Texas. This is Ericsson's first US silicon design center so we're assembling a team from scratch to create the silicon designs that will power Ericsson's new generation of 5G network infrastructure products. 5G is the future of communications and this new, tightly-knit team will ensure networks have the processing power to deliver on the promises of a connected society.
Would you like to work with the latest FinFET technology? Are you interested in creating the silicon engine that will enable self-driving cars, smart cities, and all things IoT? Can you see yourself on a growing team where you actually know everyone's name? Do you want to work on amazing things but still enjoy a happy work/life balance?
The ASIC Design team at Ericsson is responsible for pre-silicon Digital ASIC and SoC development for all existing and future mobile standards, including 5G. The development is done in close collaboration with internal and external stake holders such as standardization teams and market leading silicon vendors and ASIC Design houses. We are working with state of the art SI-technologies, EDA tools and methodologies.
Since we're growing this group from the ground up there are a number of current opportunities for Experienced, Creative and Innovative engineers to join this extraordinary team. These roles present a unique opportunity to work and gain competence in several areas such as modeling (TLM), RTL-design and verification, systemization, integration, synthesis, timing and SW development. Picture yourself as a key member of a diverse, dynamic team with opportunities for learning and trying out new roles and responsibilities plus much more.
You have successfully delivered microarchitecture/RTL blocks for complex multi-core ASIC/SoC/FPGA. You work daily with Verilog/System Verilog/UVM. You have a great interest in learning new things every day and want to make a difference. You have a very positive attitude and flourish with new challenges. You are keen to tackle problems and do so creatively. Where there is change you see opportunities. You are a great teammate and a very communicative person but you also work well independently. You make sure to reach results with high quality and on time.
Minimum of 5 years working experience designing RTL blocks
ASIC, SoC or FPGA design and/or verification/simulation at sub-system and/or chip level
Fluent in Verilog/System Verilog, VHDL a plus
Fluent in English, speaking and writing
Synthesis and Timing analysis for ASIC
Multi/Many Core CPU Architecture Knowledge
IT Environment like Linux, Clearcase, LSF
Experience from verification in lab
DISCLAIMER: The above statements are intended to describe the general nature and level of work being performed by employees assigned to this classification. They are not intended to be construed as an exhaustive list of all responsibilities, duties and skills required of employees assigned to this position. Therefore employees assigned may be required to perform additional job tasks required by the manager.
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Primary country and city: United States (US) || || Austin || IT
Req ID: 205947