Asic Design Verification Engineer

Google Inc. Sunnyvale , CA 94089

Posted 5 days ago

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

You will use your design and verification expertise to verify complex digital designs. You will collaborate closely with design and verification engineers in active projects and perform hands-on verification. Using your UVM and SystemVerilog coding and problem solving skills, you will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will be responsible for the full life cycle of verification, from verification planning to test execution, to collecting and closing coverage.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We're always on call to keep our networks up and running, ensuring our users have the best and fastest experience possible.

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering or related field, or equivalent practical experience.

  • Experience or knowledge of verification methodologies such as UVM/OVM/VMM.

  • Experience or knowledge with SystemVerilog, SVA or functional coverage.

Preferred qualifications:

  • MS or PhD degree in Electrical Engineering.

  • Experienced with the full verification life cycle.

  • Knowledge of and experience with industry-standard simulators, revision control systems and regression systems.

  • Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.

  • Create a constrained-random verification environment using SystemVerilog and UVM.

  • Identify and write all types of coverage measures for stimulus and corner-cases.

  • Debug tests with design engineers to deliver functionally correct design blocks.

  • Close coverage measures to identify verification holes and to show progress towards tape-out.

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