Job Title: Array/ Register File Design
Basic knowledge and experience in designing high density and high frequency memory arrays using Cadence Tool Suite. The candidate should possess custom circuit design skills in order to design memory cells for different technology nodes with good understanding of deciding the number of bits/entries, positioning the cells for effective circuit and layout performance, resolving all the timing and structural issues(related to precharge/evaluation/local bit line/global bitline) in the memory cells and ensuring the cells meets all the circuit parameters given in the project. Experience in advanced technology nodes required.
Good Experience in working on domino circuits and resolving timing issues related to domino circuits.
Should have experience designing memory cells of different sizes and complexities. Good knowledge of understanding the floorplan at subsystem and full chip level and make decisions for the size of the memory arrays.
Should have good understanding of the custom layout to work with the layout designer on these memory cells.
Good experience of resolving complex timing issues, layout verification and other flows necessary for tapeout.
Good knowledge of all the physical design flows from understanding RTL through tapeout.
Ability to independently handle complex blocks to closure.
Excellent verbal and communication skills. Good leadership skills and ability to handle a team independently.
Array, RF, Cadence, Domino circuits
HCL America Inc.